Pradeepkumar.org

Requirements:

WARP
Active HDL

 
Program for Shift Register: library IEEE; use IEEE.std_logic_1164.all; entity shiftreg is port ( load: in STD_LOGIC; [...]

Continue reading Shift Register

Requirements:

WARP
Active HDL
Cool Runner and Fitter CPLD Kit

 
Program for Magnitude Comparator library IEEE; use IEEE.std_logic_1164.all; entity mag_comp is port ( a: in STD_LOGIC_VECTOR [...]

Continue reading 4 bit Magnitude Comparator

Requirements:

WARP
Active HDL
Cool Runner and Fitter CPLD Kit

Program for Asynchronous counter: Library ieee; Use ieee.std_logic_1164.all; entity asyn_counter is port ( clk: in BIT; [...]

Continue reading Simulation of Synchronous and Asynchronous counters

Requirements:

WARP
Active HDL

Design:
 

Program for the Look Ahead Carry Generator library IEEE; use IEEE.std_logic_1164.all; entity look_ahead_carry is port ( a: in STD_LOGIC_VECTOR (4 downto [...]

Continue reading Simulation of Look Ahead Carry Generator

Requirements:

WARP
Active HDL

Procedure:

The Specification of the BCD to GRAY Code Converter is taken.
The input and the output ports of the above specification are defined to a Standard language (std_logic). The temporary variables are selected if necessary.
Entity and Architecture is created for the above specification.
The Result is verified by simulation and the [...]

Continue reading Simulation of BCD to Gray Code Conversion

Requirements:

WARP
Active HDL

Procedure:

The Specifications of the Baud Rate are chosen.
The input and the output ports of the above specification are defined to a Standard language (std_logic). The temporary variables are selected if necessary.
Entity and Architecture is created for the above specification.
The Result is verified by simulation and the waveforms are seen. [...]

Continue reading Baud Rate Generator

Requirements:

WARP
Active HDL

Procedure:

The Specifications of the Baud Rate are chosen.
The input and the output ports of the above specification are defined to a Standard language (std_logic). The temporary variables are selected if necessary.
Entity and Architecture is created for the above specification.
The Result is verified by simulation and the waveforms are [...]

Continue reading Simulation of Arithmetic and Logic Unit (ALU)

Requirements:

WARP
Active HDL
Cool Runner and Fitter CPLD Kit

D Flip Flop

 
Program for D Flip flop Library ieee; Use ieee.std_logic_1164.all; entity dff is port ( [...]

Continue reading Simulation of D Flip Flop and J-K Flip Flop