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Synchronous Data Flow Graph (SDFG)The Synchronous DFG is similar to a directed graph which contains vertices and edges. Where each vertex represents the computation and the edges do the job of carrying the data from one vertex to anotherVertex is represented by a circle whereas the edge is denoted as an arrow.
Homogeneous Synchronous DFG [...]

Continue reading Modeling Multiprocessor Systems

· It is a powerful tool for Real Time Embedded systems· It is a graphical modeling tool suggested by C A Petri· Used in designing the algorithms for control circuits, computational and communication operators· FSM is used when there are finite number of states and petri nets are used when the number of states is [...]

Continue reading Petri Net Model

Examples include:· Telephone with states – idle, receiving a ring, dialing, connected· Washing Machine with states – washing, rinsing, drying· Timers with states- idle, start, running1) Inputs to the process changes the state to a new state. The process change from one state to another state is called as transition2) A state can receive multiple [...]

Continue reading Finite State Machines (FSM) Models

Modelling Processes for Software Analysis before Software ImplementationData Flow Graph (DFG)

Data Flow Graph (DFG) as the name says only the data which is flowing in to a process taken into account. for example going to a bank for depositing the cash includes the data 1) input is account number and 2) output data is balance [...]

Continue reading Program Modelling Concepts

Sources of Interrupts

Software Error Related Sources:

Overflow
Underflow
Division by zero
Illegal opcode
Programmer defined exceptions

Software code related sources

Breakpoint
Debugging trap
RTC driven software timer
Input driven software timer
Semaphore take and release
Even related
Task blocking overflow
Task finished timeouts

Internal Hardware device sources

Parallel port and UART serial receiver port
UART transmission complete
ADC Start of conversion and End of Conversion
Pulse Accumulator
Real Time Clock
Watch Dog Timer Reset
Timer overflow [...]

Continue reading Interrupt Servicing (Handling) Mechanism

Writing Device Driving ISRs in a System

A device has three sets of device registers

Data Register
Control Register
Status register

A device initializes by setting the control register bit and the device closes b y resetting the control register bits.
There may be more than one device register at a device address.
Control register bits controls all the action of the [...]

Continue reading Device Driving ISRs in a System

1. A device has 3 set of registers

Data Register
Control Register (controls all actions of the device)
Status Register (reflects the flags for the status of the device at an instant and changes after performing the actions as per device drivers)

2. A device initializes by setting the control register bit and the device closes by resetting the [...]

Continue reading Device Driving ISRs